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ds05-20907-3e fujitsu semiconductor data sheet flash memory cmos 32 m (4m 8/2m 16) bit mirrorflash tm * mbm29pl32tm/bm 90/10 n description the mbm29pl32tm/bm is a 32m-bit, 3.0 v-only flash memory organized as 4m bytes by 8 bits or 2m words by 16 bits. the mbm29pl32tm/bm is offered in 48-pin tsop(1) and 48-ball fbga. the device is designed to be programmed in-system with the standard 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the devices can also be reprogrammed in standard eprom programmers. (continued) n product line up n packages * : mirrorflash tm is a trademark of fujitsu limited. note s : programming in byte mode ( 8 ) is prohibited. programming to the address that already contains data is prohibited . (it is mandatory to erase data prior to overprogram on the same address.) part no. mbm29pl32tm/bm 90 10 v cc 3.0 v to 3.6 v 3.0 v to 3.6 v max address access time 90 ns 100 ns max ce access time 90 ns 100 ns max page read access time 25 ns 30 ns 48-pin plastic tsop (1) 48-ball plastic fbga (fpt-48p-m19) (bga-48p-m20)
mbm29pl32tm/bm 90/10 2 (continued) the standard mbm29pl32tm/bm offers access times of 90 ns, allowing operation of high-speed microproces- sors without wait states. to eliminate bus contention the devices have separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29pl32tm/bm supports command set compatible with jedec single-power-supply eeproms stan- dard. commands are written into the command register. the register contents serve as input to an internal state- machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the devices is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the mbm29pl32tm/bm is programmed by executing the program command sequence. this will invoke the embedded program algorithm tm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm tm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. all sectors are erased when shipped from the factory. the device features single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 . once the end of a program or erase cycle has been completed, the devices internally return to the read mode. fujitsu flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the devices electrically erase all bits within a sector simulta- neously via hot-hole assisted erase. the words are programmed one word at a time using the eprom program- ming mechanism of hot electron injection.
mbm29pl32tm/bm 90/10 3 n features ? 0.23 m m m m m process technology ? single 3.0 v read, program and erase minimizes system level power requirements ? industry-standard pinouts 48-pin tsop (1) (package suffix: tn - normal bend type) 48-ball fbga(package suffix: pbt) ? minimum 100,000 program/erase cycles ? high performance page mode fast 8 bytes / 4 words access capability ? sector erase architecture eight 8k byte and sixty-three 64k byte sectors eight 4k word and sixty-three 32k word sectors any combination of sectors can be concurrently erased. also supports full chip erase ? boot code sector architecture t = top sector b = bottom sector ? hiddenrom 256 bytes / 128 words of hiddenrom, accessible through a hiddenrom entry command sequence factory serialized and protected to provide a secure electronic serial number (esn) ? wp /acc input pin at v il , allows protection of outermost two 8k bytes / 4k words sectors, regardless of sector protection/unpro- tection status at v acc , increases program performance ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm * algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switches themselves to low power mode ? program suspend/resume suspends the program operation to allow a read in another address ? low v cc write inhibit 2.5 v ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? sector group protection hardware method disables any combination of sector groups from program or erase operations ? sector group protection set function by extended sector protect command ? fast programming function by extended command ? temporary sector group unprotection temporary sector group unprotection via the reset pin this feature allows code changes in previously locked sectors ? in accordance with cfi (c ommon f lash memory i nterface) * : embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mbm29pl32tm/bm 90/10 4 n pin assignments a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 a 20 we reset n.c. wp/acc ry/by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-pin plastic tsop(1) a 16 byte v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce a 0 (marking side) (fpt-48p-m19) (top view) a6 b6 c6 d6 e6 f6 byte g6 h6 a5 b5 c5 d5 e5 f5 g5 h5 a 9 a 8 a 10 a 11 dq 7 dq 14 dq 13 dq 6 a4 b4 c4 d4 e4 f4 g4 h4 we reset n.c. a 19 dq 5 dq 12 v cc dq 4 a3 b3 c3 d3 e3 f3 g3 h3 ry/by wp/ acc a 18 a 20 dq 2 dq 10 dq 11 dq 3 a2 b2 c2 d2 e2 f2 g2 h2 a 7 a 17 a 6 a 5 dq 0 dq 8 dq 9 dq 1 a1 b1 c1 d1 e1 f1 g1 h1 a 3 a 4 a 2 a 1 a 0 ce oe v ss a 13 a 12 a 14 a 15 a 16 dq 15 / a -1 v ss 48-ball plastic fbga (top view) marking side (bga-48p-m20)
mbm29pl32tm/bm 90/10 5 n pin descriptions mbm29pl32tm/bm pin configuration pin function a 20 to a 0 , a -1 address inputs dq 15 to dq 0 data inputs/outputs ce chip enable oe output enable we write enable wp /acc hardware write protection/program acceleration reset hardware reset pin/temporary sector group unprotection byte select byte or word mode ry/by ready/busy output v cc device power supply v ss device ground n.c. no internal connection
mbm29pl32tm/bm 90/10 6 n block diagram n logic symbol v ss v cc we ce a 1 , a 0 oe erase voltage generator dq 15 to dq 0 state control command register program voltage generator address latch x-decoder y-decoder cell matrix y-gating chip enable output enable logic data latch stb stb reset wp/ acc timer for program/erase input/output buffers a 20 to a 2 byte (a- 1 ) 21 a 20 to a 0 we oe ce dq 15 to dq 0 wp/acc reset 16 or 8 byte ry/by a -1
mbm29pl32tm/bm 90/10 7 n device bus operation mbm29pl32tm/bm user bus operations (word mode : byte = v ih ) legend : l = v il , h = v ih , x = v il or v ih . see n electrical characteristics 1. dc characteristics for voltage levels. hi-z = high-z, v id = 11.5 v to 12.5 v *1 : manufacturer and device codes may also be accessed via a command register write sequence. see sector group protection verify autoselect codes. *2 : refer to sector group protection in n functional description. *3 : d in or d out as required by command sequence, data pulling, or sector protect algorithm *4 : if wp /acc = v il , the outermost two sectors remain protected. if wp /acc = v ih , the outermost two sectors will be protected or unprotected as determined by the method specified in sector group protection in n functional description. operation ce oe we a 0 a 1 a 2 a 3 a 6 a 9 dq 0 to dq 15 reset wp / acc standby h x x x x x x x x hi-z h x autoselect manufacture code* 1 llhlllllv id code h x autoselect device code* 1 llhhllllv id code h x read l l h a 0 a 1 a 2 a 3 a 6 a 9 d out hx output disable l h h x x x x x x hi-z h x write (program/erase) l h l a 0 a 1 a 2 a 3 a 6 a 9 *3 h *4 enable sector group protection* 2 lhllhlllx *3 v id h temporary sector group unprotection xxxxxxxxx *3 v id h reset (hardware) x x x x x x x x x hi-z l x sector write protection x x x x x x x x x x h l
mbm29pl32tm/bm 90/10 8 mbm29pl32tm/bm user bus operations (byte mode : byte = v il ) legend : l = v il , h = v ih , x = v il or v ih . see n electrical characteristics 1. dc characteristics for voltage levels. hi-z = high-z, v id = 11.5 v to 12.5 v *1 : manufacturer and device codes may also be accessed via a command register write sequence. see mbm29pl32tm/bm standard command definitions. *2 : refer to sector group protection. *3 : d in or d out as required by command sequence, data pulling, or sector protect algorithm *4 : if wp /acc = v il , the outermost two sectors remain protected. if wp /acc = v ih , the outermost two sectors will be protected or unprotected as determined by the method specified in sector group protection in page 23. operation ce oe we dq 15 / a -1 a 0 a 1 a 2 a 3 a 6 a 9 dq 0 to dq 7 reset wp / acc standby h x x x x x x x x x hi-z h x autoselect manufacture code* 1 llh l lllllv id code h x autoselect device code* 1 llh l hllllv id code h x read l l h a -1 a 0 a 1 a 2 a 3 a 6 a 9 d out hx output disable l h h x x x x x x x hi-z h x write (erase) l h l a -1 a 0 a 1 a 2 a 3 a 6 a 9 *3 h *4 enable sector group protection* 2 lhl l lhlllx *3 v id h temporary sector group unprotection xxxxxxxxxx*3 v id h reset (hardware) x x x x x x x x x x hi-z l x sector write protection x x x x x x x x x x x h l
mbm29pl32tm/bm 90/10 9 mbm29pl32tm/bm standard command definitions* 1 (continued) command sequence bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data reset* 2 word/ byte 1 xxxhf0h reset* 2 word 3 555h aah 2aah 55h 555h f0h ra * 13 rd * 13 byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h 555h 90h 00h * 13 04h* 13 byte aaah 555h aaah program word 4 555h aah 2aah 55h 555h a0h pa pd chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h program/erase suspend* 3 1 xxxhb0h program/erase resume* 3 1 xxxh30h set to fast mode* 4 word 3 555h aah 2aah 55h 555h 20h byte aaah 555h aaah fast program* 4 word 2 xxxh a0h pa pd reset from fast mode* 5 word/ byte 2 xxxh 90h xxxh 00h * 12 write to buffer word 20 555h aah 2aah 55h sa 25h sa 0fh pa pd wbl pd byte aaah 555h program buffer to flash (confirm) 1 sa29h write to buffer abort reset* 6 word 3 555h aah 2aah 55h 555h f0h byte aaah 555h aaah extended sector group protection * 7, * 8 word 4 xxxh 60h sga 60h sga 40h sga * 13 sd * 13 byte query* 9 word 1 55h 98h byte aah hiddenrom entry* 10 word 3 555h aah 2aah 55h 555h 88h byte aaah 555h aaah hiddenrom program * 10, * 11 word 4 555h aah 2aah 55h 555h a0hpapd byte aaah 555h aaah hiddenrom exit* 11 word 4 555h aah 2aah 55h 555h 90h xxxh 00h byte aaah 555h aaah
mbm29pl32tm/bm 90/10 10 (continued) legend : address bits a 20 to a 11 = x = h or l for all address commands except for program address (pa), sector address (sa) and sector group address (sga). bus operations are defined in mbm29pl32tm/bm user bus operations (word mode : byte = v ih ) and mbm29pl32tm/bm user bus operations (byte mode : byte = v il ). ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the write pulse. sa = address of the sector to be programmed / erased. the combination of a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 will uniquely select any sector. see sector address table (mbm29pl32tm) and sector address table (mbm29pl32bm). sga = sector group address to be protected. see sector group address table (mbm29pl32tm) and sector group address table (mbm29pl32bm). rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of write plus. wbl = write buffer location hra = address of the hiddenrom area ; mbm29pl32tm (top boot type)word mode : 1fff7fh to 1fffffh byte mode : 3ffeffh to 3fffffh mbm29pl32bm (bottom boot type)word mode : 000000h to 00007fh byte mode : 000000h to 0000ffh *1 : the command combinations not described in mbm29pl32tm/bm standard command definitions are illegal. *2 : both of these reset commands are equivalent except for "write to buffer abort" reset. *3 : the erase suspend and erase resume command are valid only during a sector erase operation. *4 : the set to fast mode command is required prior to the fast program command. *5 : the reset from fast mode command is required to return to the read mode when the device is in fast mode. *6 : reset to the read mode. the write to buffer abort reset command is required after the write to buffer operation was aborted. *7 : this command is valid while reset = v id . *8 : sector group address (sga) with a 6 = 0, a 3 = 0, a 2 = 0, a 1 = 1, and a 0 = 0 *9 : the valid address are a 6 to a 0 . *10 : the hiddenrom entry command is required prior to the hiddenrom programming. *11 : this command is valid during hiddenrom mode. *12 : the data f0h is also acceptable. *13 : indicates read cycle.
mbm29pl32tm/bm 90/10 11 sector group protection verify autoselect codes *1 : a -1 is for byte mode. *2 : at word mode, a read cycle at address 01h ( at byte mode, 02h ) outputs device code. when 227eh ( at byte mode, 7eh ) is output, it indicates that reading two additional codes, called extended device codes, will be required. therefore the system may continue reading out these extended device codes at the address of 0eh ( at byte mode, 1ch ), as well as at 0fh ( at byte mode, 1eh ). *3 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *4 : toggle ce , provided sga = fix and we = fix. the data in the first cycle is invalid. the data in the second one is valid. type a 20 to a 12 a 6 a 3 a 2 a 1 a 0 a -1 * 1 code (hex) manufacturers code x v il v il v il v il v il v il 04h device code word xv il v il v il v il v ih x 227eh byte v il 7eh extended device code* 2 mbm29pl32tm word xv il v ih v ih v ih v il x 221ah byte v il 1ah word xv il v ih v ih v ih v ih x 2201h byte v il 01h mbm29pl32bm word xv il v ih v ih v ih v il x 221ah byte v il 1ah word xv il v ih v ih v ih v ih x 2200h byte v il 00h sector group protection* 4 sector group addresses v il v il v il v ih v il v il *3
mbm29pl32tm/bm 90/10 12 sector address table (mbm29pl32tm) (continued) sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sa0 000000xxx 64/32 0 00000h to 00ffffh 000000h to 007fffh sa1 000001xxx 64/32 0 10000h to 01ffffh 008000h to 00ffffh sa2 000010xxx 64/32 0 20000h to 02ffffh 010000h to 017fffh sa3 000011xxx 64/32 0 30000h to 03ffffh 018000h to 01ffffh sa4 000100xxx 64/32 0 40000h to 04ffffh 020000h to 027fffh sa5 000101xxx 64/32 0 50000h to 05ffffh 028000h to 02ffffh sa6 000110xxx 64/32 0 60000h to 06ffffh 030000h to 037fffh sa7 000111xxx 64/32 0 70000h to 07ffffh 038000h to 03ffffh sa8 001000xxx 64/32 0 80000h to 08ffffh 040000h to 047fffh sa9 001001xxx 64/32 0 90000h to 09ffffh 048000h to 04ffffh sa10001010xxx 64/32 0a0000h to 0affffh 05 0000h to 057fffh sa11001011xxx 64/32 0b0000h to 0bffffh 05 8000h to 05ffffh sa12001100xxx 64/32 0c0000h to 0cffffh 06 0000h to 067fffh sa13001101xxx 64/32 0d0000h to 0dffffh 06 8000h to 06ffffh sa14001110xxx 64/32 0e0000h to 0effffh 07 0000h to 077fffh sa15001111xxx 64/32 0f0000h to 0fffffh 07 8000h to 07ffffh sa16010000xxx 64/32 1 00000h to 10ffffh 080000h to 087fffh sa17010001xxx 64/32 1 10000h to 11ffffh 088000h to 08ffffh sa18010010xxx 64/32 1 20000h to 12ffffh 090000h to 097fffh sa19010011xxx 64/32 1 30000h to 13ffffh 098000h to 09ffffh sa20010100xxx 64/32 1 40000h to 14ffffh 0a0000h to 0a7fffh sa21010101xxx 64/32 1 50000h to 15ffffh 0a8000h to 0affffh sa22010110xxx 64/32 1 60000h to 16ffffh 0b0000h to 0b7fffh sa23010111xxx 64/32 1 70000h to 17ffffh 0b8000h to 0bffffh sa24011000xxx 64/32 1 80000h to 18ffffh 0c0000h to 0c7fffh sa25011001xxx 64/32 1 90000h to 19ffffh 0c8000h to 0cffffh sa26011010xxx 64/32 1a0000h to 1affffh0d 0000h to 0d7fffh sa27011011xxx 64/32 1b0000h to 1bffffh0d 8000h to 0dffffh sa28011100xxx 64/32 1c0000h to 1cffffh0e 0000h to 0e7fffh sa29011101xxx 64/32 1d0000h to 1dffffh0e 8000h to 0effffh sa30011110xxx 64/32 1e0000h to 1effffh 0f 0000h to 0f7fffh sa31011111xxx 64/32 1f0000h to 1fffffh 0f 8000h to 0fffffh
mbm29pl32tm/bm 90/10 13 (continued) sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sa32 1 0 0 0 0 0 x x x 64/32 200000h to 20ffffh 100000h to 107fffh sa33 1 0 0 0 0 1 x x x 64/32 210000h to 21ffffh 108000h to 10ffffh sa34 1 0 0 0 1 0 x x x 64/32 220000h to 22ffffh 110000h to 117fffh sa35 1 0 0 0 1 1 x x x 64/32 230000h to 23ffffh 118000h to 11ffffh sa36 1 0 0 1 0 0 x x x 64/32 240000h to 24ffffh 120000h to 127fffh sa37 1 0 0 1 0 1 x x x 64/32 250000h to 25ffffh 128000h to 12ffffh sa38 1 0 0 1 1 0 x x x 64/32 260000h to 26ffffh 130000h to 137fffh sa39 1 0 0 1 1 1 x x x 64/32 270000h to 27ffffh 138000h to 13ffffh sa40 1 0 1 0 0 0 x x x 64/32 280000h to 28ffffh 140000h to 147fffh sa41 1 0 1 0 0 1 x x x 64/32 290000h to 29ffffh 148000h to 14ffffh sa42 1 0 1 0 1 0 x x x 64/32 2a0000h to 2affffh 150000h to 157fffh sa43 1 0 1 0 1 1 x x x 64/32 2b0000h to 2bffffh 158000h to 15ffffh sa44 1 0 1 1 0 0 x x x 64/32 2c0000h to 2cffffh 160000h to 167fffh sa45 1 0 1 1 0 1 x x x 64/32 2d0000h to 2dffffh 168000h to 16ffffh sa46 1 0 1 1 1 0 x x x 64/32 2e0000h to 2effffh 170000h to 177fffh sa47 1 0 1 1 1 1 x x x 64/32 2f0000h to 2fffffh 178000h to 17ffffh sa48 1 1 0 0 0 0 x x x 64/32 300000h to 30ffffh 180000h to 187fffh sa49 1 1 0 0 0 1 x x x 64/32 310000h to 31ffffh 188000h to 18ffffh sa50 1 1 0 0 1 0 x x x 64/32 320000h to 32ffffh 190000h to 197fffh sa51 1 1 0 0 1 1 x x x 64/32 330000h to 33ffffh 198000h to 19ffffh sa52 1 1 0 1 0 0 x x x 64/32 340000h to 34ffffh 1a0000h to 1a7fffh sa53 1 1 0 1 0 1 x x x 64/32 350000h to 35ffffh 1a8000h to 1affffh sa54 1 1 0 1 1 0 x x x 64/32 360000h to 36ffffh 1b0000h to 1b7fffh sa55 1 1 0 1 1 1 x x x 64/32 370000h to 37ffffh 1b8000h to 1bffffh sa56 1 1 1 0 0 0 x x x 64/32 380000h to 38ffffh 1c0000h to 1c7fffh sa57 1 1 1 0 0 1 x x x 64/32 390000h to 39ffffh 1c8000h to 1cffffh sa58 1 1 1 0 1 0 x x x 64/32 3a0000h to 3affffh 1d0000h to 1d7fffh sa59 1 1 1 0 1 1 x x x 64/32 3b0000h to 3bffffh 1d8000h to 1dffffh sa60 1 1 1 1 0 0 x x x 64/32 3c0000h to 3cffffh 1e0000h to 1e7fffh sa61 1 1 1 1 0 1 x x x 64/32 3d0000h to 3dffffh 1e8000h to 1effffh sa62 1 1 1 1 1 0 x x x 64/32 3e0000h to 3effffh 1f0000h to 1f7fffh sa63 1 1 1 1 1 1 0 0 0 8/4 3f0000h to 3f1fffh 1f8000h to 1f8fffh sa64 1 1 1 1 1 1 0 0 1 8/4 3f2000h to 3f3fffh 1f9000h to 1f9fffh
mbm29pl32tm/bm 90/10 14 (continued) note : the address range is a 20 to a -1 if in byte mode (byte = v il ) . the address range is a 20 to a 0 if in word mode (byte = v ih ) . sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sa65111111010 8/4 3f 4000h to 3f5fffh 1fa000h to 1fafffh sa66111111011 8/4 3f 6000h to 3f7fffh 1fb000h to 1fbfffh sa67111111100 8/4 3f 8000h to 3f9fffh 1fc000h to 1fcfffh sa68111111101 8/4 3fa000h to 3fbfffh1fd0 00h to 1fdfffh sa69111111110 8/4 3fc000h to 3fdfffh1fe0 00h to 1fefffh sa70111111111 8/4 3fe000h to 3fffffh1ff0 00h to 1fffffh
mbm29pl32tm/bm 90/10 15 sector address table (mbm29pl32bm) (continued) sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sa70 1 1 1 1 1 1 x x x 64/32 3f0000h to 3fffffh 1f8000h to 1fffffh sa69 1 1 1 1 1 0 x x x 64/32 3e0000h to 3effffh 1f0000h to 1f7fffh sa68 1 1 1 1 0 1 x x x 64/32 3d0000h to 3dffffh 1e8000h to 1effffh sa67 1 1 1 1 0 0 x x x 64/32 3c0000h to 3cffffh 1e0000h to 1e7fffh sa66 1 1 1 0 1 1 x x x 64/32 3b0000h to 3bffffh 1d8000h to 1dffffh sa65 1 1 1 0 1 0 x x x 64/32 3a0000h to 3affffh 1d0000h to 1d7fffh sa64 1 1 1 0 0 1 x x x 64/32 390000h to 39ffffh 1c8000h to 1cffffh sa63 1 1 1 0 0 0 x x x 64/32 380000h to 38ffffh 1c0000h to 1c7fffh sa62 1 1 0 1 1 1 x x x 64/32 370000h to 37ffffh 1b8000h to 1bffffh sa61 1 1 0 1 1 0 x x x 64/32 360000h to 36ffffh 1b0000h to 1b7fffh sa60 1 1 0 1 0 1 x x x 64/32 350000h to 35ffffh 1a8000h to 1affffh sa59 1 1 0 1 0 0 x x x 64/32 340000h to 34ffffh 1a0000h to 1a7fffh sa58 1 1 0 0 1 1 x x x 64/32 330000h to 33ffffh 198000h to 19ffffh sa57 1 1 0 0 1 0 x x x 64/32 320000h to 32ffffh 190000h to 197fffh sa56 1 1 0 0 0 1 x x x 64/32 310000h to 31ffffh 188000h to 18ffffh sa55 1 1 0 0 0 0 x x x 64/32 300000h to 30ffffh 180000h to 187fffh sa54 1 0 1 1 1 1 x x x 64/32 2f0000h to 2fffffh 178000h to 17ffffh sa53 1 0 1 1 1 0 x x x 64/32 2e0000h to 2effffh 170000h to 177fffh sa52 1 0 1 1 0 1 x x x 64/32 2d0000h to 2dffffh 168000h to 16ffffh sa51 1 0 1 1 0 0 x x x 64/32 2c0000h to 2cffffh 160000h to 167fffh sa50 1 0 1 0 1 1 x x x 64/32 2b0000h to 2bffffh 158000h to 15ffffh sa49 1 0 1 0 1 0 x x x 64/32 2a0000h to 2affffh 150000h to 157fffh sa48 1 0 1 0 0 1 x x x 64/32 290000h to 29ffffh 148000h to 14ffffh sa47 1 0 1 0 0 0 x x x 64/32 280000h to 28ffffh 140000h to 147fffh sa46 1 0 0 1 1 1 x x x 64/32 270000h to 27ffffh 138000h to 13ffffh sa45 1 0 0 1 1 0 x x x 64/32 260000h to 26ffffh 130000h to 137fffh sa44 1 0 0 1 0 1 x x x 64/32 250000h to 25ffffh 128000h to 12ffffh sa43 1 0 0 1 0 0 x x x 64/32 240000h to 24ffffh 120000h to 127fffh sa42 1 0 0 0 1 1 x x x 64/32 230000h to 23ffffh 118000h to 11ffffh sa41 1 0 0 0 1 0 x x x 64/32 220000h to 22ffffh 110000h to 117fffh sa40 1 0 0 0 0 1 x x x 64/32 210000h to 21ffffh 108000h to 10ffffh sa39 1 0 0 0 0 0 x x x 64/32 200000h to 20ffffh 100000h to 107fffh sa38 0 1 1 1 1 1 x x x 64/32 1f0000h to 1fffffh 0f8000h to 0fffffh
mbm29pl32tm/bm 90/10 16 (continued) sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sa37011110xxx 64/32 1e0000h to 1effffh 0f 0000h to 0f7fffh sa36011101xxx 64/32 1d0000h to 1dffffh0e8 000h to 0effffh sa35011100xxx 64/32 1c0000h to 1cffffh0e 0000h to 0e7fffh sa34011011xxx 64/32 1b0000h to 1bffffh0d8 000h to 0dffffh sa33011010xxx 64/32 1a0000h to 1affffh0d 0000h to 0d7fffh sa32011001xxx 64/32 1 90000h to 19ffffh 0c8000h to 0cffffh sa31011000xxx 64/32 1 80000h to 18ffffh 0c0000h to 0c7fffh sa30010111xxx 64/32 1 70000h to 17ffffh 0b8000h to 0bffffh sa29010110xxx 64/32 1 60000h to 16ffffh 0b0000h to 0b7fffh sa28010101xxx 64/32 1 50000h to 15ffffh 0a8000h to 0affffh sa27010100xxx 64/32 1 40000h to 14ffffh 0a0000h to 0a7fffh sa26010011xxx 64/32 1 30000h to 13ffffh 098000h to 09ffffh sa25010010xxx 64/32 1 20000h to 12ffffh 090000h to 097fffh sa24010001xxx 64/32 1 10000h to 11ffffh 088000h to 08ffffh sa23010000xxx 64/32 1 00000h to 10ffffh 080000h to 087fffh sa22001111xxx 64/32 0f0000h to 0fffffh 078 000h to 07ffffh sa21001110xxx 64/32 0e0000h to 0effffh 07 0000h to 077fffh sa20001101xxx 64/32 0d0000h to 0dffffh068 000h to 06ffffh sa19001100xxx 64/32 0c0000h to 0cffffh 06 0000h to 067fffh sa18001011xxx 64/32 0b0000h to 0bffffh 058 000h to 05ffffh sa17001010xxx 64/32 0a0000h to 0affffh 05 0000h to 057fffh sa16001001xxx 64/32 0 90000h to 09ffffh 048000h to 04ffffh sa15001000xxx 64/32 0 80000h to 08ffffh 040000h to 047fffh sa14000111xxx 64/32 0 70000h to 07ffffh 038000h to 03ffffh sa13000110xxx 64/32 0 60000h to 06ffffh 030000h to 037fffh sa12000101xxx 64/32 0 50000h to 05ffffh 028000h to 02ffffh sa11000100xxx 64/32 0 40000h to 04ffffh 020000h to 027fffh sa10000011xxx 64/32 0 30000h to 03ffffh 018000h to 01ffffh sa9 000010xxx 64/32 0 20000h to 02ffffh 010000h to 017fffh sa8 000001xxx 64/32 0 10000h to 01ffffh 008000h to 00ffffh sa7 000000111 8/4 00e 000h to 00ffffh 007000h to 007fffh sa6 000000110 8/4 00c0 00h to 00dfffh 006000h to 006fffh sa5 000000101 8/4 00a0 00h to 00bfffh 005000h to 005fffh
mbm29pl32tm/bm 90/10 17 (continued) note : the address range is a 20 to a -1 if in byte mode (byte = v il ) . the address range is a 20 to a 0 if in word mode (byte = v ih ) . sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sa4 000000100 8/4 0 08000h to 009fffh 004000h to 004fffh sa3 000000011 8/4 0 06000h to 007fffh 003000h to 003fffh sa2 000000010 8/4 0 04000h to 005fffh 002000h to 002fffh sa1 000000001 8/4 0 02000h to 003fffh 001000h to 001fffh sa0 000000000 8/4 0 00000h to 001fffh 000000h to 000fffh
mbm29pl32tm/bm 90/10 18 sector group address table (mbm29pl32tm) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 0 0 0 0 x x x x x sa0 to sa3 sga1 0 0 0 1 x x x x x sa4 to sa7 sga2 0 0 1 0xxxxx sa8 to sa11 sga3 0 0 1 1 x x x x x sa12 to sa15 sga4 0 1 0 0 x x x x x sa16 to sa19 sga5 0 1 0 1 x x x x x sa20 to sa23 sga6 0 1 1 0 x x x x x sa24 to sa27 sga7 0 1 1 1 x x x x x sa28 to sa31 sga8 1 0 0 0 x x x x x sa32 to sa35 sga9 1 0 0 1 x x x x x sa36 to sa39 sga10 1 0 1 0 x x x x x sa40 to sa43 sga11 1 0 1 1 x x x x x sa44 to sa47 sga12 1 1 0 0 x x x x x sa48 to sa51 sga13 1 1 0 1 x x x x x sa52 to sa55 sga14 1 1 1 0 x x x x x sa56 to sa59 sga15 1 1 1 1 00 x x x sa60 to sa62 01 10 sga16 1 1 1 1 1 1 0 0 0 sa63 sga17 1 1 1 1 1 1 0 0 1 sa64 sga18 1 1 1 1 1 1 0 1 0 sa65 sga19 1 1 1 1 1 1 0 1 1 sa66 sga20 1 1 1 1 1 1 1 0 0 sa67 sga21 1 1 1 1 1 1 1 0 1 sa68 sga22 1 1 1 1 1 1 1 1 0 sa69 sga23 1 1 1 1 1 1 1 1 1 sa70
mbm29pl32tm/bm 90/10 19 sector group address table (mbm29pl32bm) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 000000000 sa0 sga1 000000001 sa1 sga2 000000010 sa2 sga3 000000011 sa3 sga4 000000100 sa4 sga5 000000101 sa5 sga6 000000110 sa6 sga7 000000111 sa7 sga8 0000 01 x x x sa8 to sa10 10 11 sga9 0 0 0 1 x x x x x sa11 to sa14 sga10 0 0 1 0 x x x x x sa15 to sa18 sga11 0 0 1 1 x x x x x sa19 to sa22 sga12 0 1 0 0 x x x x x sa23 to sa26 sga13 0 1 0 1 x x x x x sa27 to sa30 sga14 0 1 1 0 x x x x x sa31 to sa34 sga15 0 1 1 1 x x x x x sa35 to sa38 sga16 1 0 0 0 x x x x x sa39 to sa42 sga17 1 0 0 1 x x x x x sa43 to sa46 sga18 1 0 1 0 x x x x x sa47 to sa50 sga19 1 0 1 1 x x x x x sa51 to sa54 sga20 1 1 0 0 x x x x x sa55 to sa58 sga21 1 1 0 1 x x x x x sa59 to sa62 sga22 1 1 1 0 x x x x x sa63 to sa66 sga23 1 1 1 1 x x x x x sa67 to sa70
mbm29pl32tm/bm 90/10 20 common flash memory interface code (continued) a 6 to a 0 dq 15 to dq 0 description 10h 11h 12h 0051h 0052h 0059h query-unique ascii string qry 13h 14h 0002h 0000h primary oem command set (02h = fujitsu standard) 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = not applicable) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = not applicable) 1bh 0027h v cc min (write/erase) dq 7 to dq 4 : 1 v/bit, dq 3 to dq 0 : 100 mv/bit 1ch 0036h v cc max (write/erase) dq 7 to dq 4 : 1 v/bit, dq 3 to dq 0 : 100 mv/bit 1dh 0000h v pp min voltage (00h = no v pp pin) 1eh 0000h v pp max voltage (00h =no v pp pin) 1fh 0007h typical timeout per single write 2 n m s 20h 0007h typical timeout for min size buffer write 2 n m s 21h 000ah typical timeout per individual sector erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms 23h 0001h max timeout for write 2 n times typical 24h 0005h max timeout for buffer write 2 n times typical 25h 0004h max timeout per individual sector erase 2 n times typical 26h 0000h max timeout for full chip erase 2 n times typical 27h 0016h device size = 2 n byte 28h 29h 0002h 0000h flash device interface description 02h : 8/ 16 2ah 2bh 0005h 0000h max number of byte in multi-byte write = 2 n 2ch 0002h number of erase block regions within device (02h = boot) 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information 31h 32h 33h 34h 003eh 0000h 0000h 0001h erase block region 2 information
mbm29pl32tm/bm 90/10 21 (continued) a 6 to a 0 dq 15 to dq 0 description 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information 40h 41h 42h 0050h 0052h 0049h query-unique ascii string pri 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0008h address sensitive unlock required 46h 0002h erase suspend (02h = to read & write) 47h 0004h number of sectors in per group 48h 0001h sector temporary unprotection (01h = supported) 49h 0004h sector protection algorithm 4ah 0000h dual operation (00h = not supported) 4bh 0000h burst mode type (00h = not supported) 4ch 0001h page mode type (01h = 4-word page supported) 4dh 00b5h v acc (acceleration) supply minimum dq 7 to dq 4 : 1 v/bit, dq 3 to dq 0 : 100 mv/bit 4eh 00c5h v acc (acceleration) supply maximum dq 7 to dq 4 : 1 v/bit, dq 3 to dq 0 : 100 mv/bit 4fh 00xxh cfi write protect (02h = bottom boot device with wp protect 03h = top boot device with wp protect) 50h 01h program suspend (01h = supported)
mbm29pl32tm/bm 90/10 22 n functional description standby mode there are two ways to implement the standby mode on the device, one using both the ce and reset pins, and the other via the reset pin only. when using both pins, cmos standby mode is achieved with ce and reset input held at v cc 0.3 v. under this condition the current consumed is less than 5 a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even when ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l) . under this condition the current consumed is less than 5 a max. once the reset pin is set high, the device requires t rh as a wake-up time for output to be valid for read access. during standby mode, the output is in the high impedance state, regardless of oe input. automatic sleep mode automatic sleep mode works to restrain power consumption during read-out of device data. it can be useful in applications such as handy terminal, which requires low power consumption. to activate this mode, the device automatically switch themselves to low power mode when the device addresses remain stable after t acc + 30 ns from data valid. it is not necessary to control ce , we , and oe in this mode. the current consumed is typically 1 m a (cmos level). since the data are latched during this mode, the data are continuously read out. when the addresses are changed, the mode is automatically canceled and the device read-out the data for changed addresses. autoselect the autoselect mode allows reading out of a binary code and identifies its manufacturer and type.it is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. to activate this mode, the programming equipment must force v id on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling a 0 . all addresses can be either high or low except a 6 , a 3 ,a 2 ,a 1 and a 0 . see mbm29pl32tm/bm user bus operations (word mode : byte = vih) and mbm29pl32tm/bm user bus operations (byte mode : byte = vil) in n device bus operation. the manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in mbm29pl32tm/bm standard command definitions in n device bus operation.refer to autoselect command section. in word mode, a read cycle from address 00h returns the manufacturers code (fujitsu = 04h) . a read cycle at address 01h outputs device code. when 227eh is output, it indicates that two additional codes, called extended device codes will be required. therefore the system may continue reading out these extended device codes at addresses of 0eh and 0fh. notice that the above applies to word mode. the addresses and codes differ from those of byte mode. refer to sector group protection verify autoselect codes in n device bus operation. read mode the device has two control functions required to obtain data at the outputs. ce is the power control and used for a device selection. oe is the output control and used to gate data to the output pins. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc -t oe time.) when reading out a data without changing addresses after power-up, input hardware reset or to change ce pin from h or l.
mbm29pl32tm/bm 90/10 23 page mode read the device is capable of fast read access for random locations within limited address location called page. the page size of the device is 8 bytes / 4 words, within the appropriate page being selected by the higher address bits a 20 to a 2 and the address bits a 1 to a 0 in word mode ( a 1 to a -1 in byte mode) determining the specific word within that page. this is an asynchronous operation with the microprocessor supplying the specific word location. the initial page access is equal to the random access (t acc ) and subsequent page read access (as long as the locations specified by the microprocessor fall within that page) is equivalent to the page address access time (t pa c c ). here again, ce selects the device and oe is the output control and should be used to gate data to the output pins if the device is selected. fast page mode, accesses are obtained by keeping a 20 to a 2 constant and changing a 1 and a 0 in word mode ( a 1 to a -1 in byte mode ) to select the specific word within that page. output disable with the oe input at logic high level (v ih ), output from the devices are disabled. this may cause the output pins to be in a high impedance state. write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the device function. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the com- mand register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever starts later; while data is latched on the rising edge of we or ce , whichever starts first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector group protection the device features hardware sector group protection. this feature will disable both program and erase opera- tions in any combination of thirty two sector groups of memory.see sector group address table (mbm29pl32tm) and sector group address table (mbm29pl32bm) in n device bus operation. the users side can use the sector group protection using programming equipment. the device is shipped with all sector groups that are unprotected. to activate it, the programming equipment must force v id on address pin a 9 and control pin oe , ce = v il and a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih . the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. sector address table (mbm29pl32tm) and sector address table (mbm29pl32bm) in n device bus operation defines the sector address for each of the seventy-one (71) individual sectors, and sector group address table (mbm29pl32tm) and sector group address table (mbm29pl32bm) in n device bus operation defines the sector group address for each of the twenty-four (24) individual group sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector group addresses must be held constant during the we pulse. see sector group protection timing diagram in n switching waveforms and sector group protection algorithm in n flow chart for sector group protection timing diagram and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the device will produce 0 for unprotected sectors. in this mode, the lower order addresses, except for a 0 , a 1 , a 2 , a 3 , and a 6 can be either high or low. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires applying to v il on byte mode. it is also possible to determine if a sector group is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses(a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) are the desired sector group address will produce a logical 1 at dq 0 for a protected sector group. see sector group protection verify autoselect codes in n device bus operation for au- toselect codes.
mbm29pl32tm/bm 90/10 24 temporary sector group unprotection this feature allows temporary unprotection of previously protected sector groups of the devices in order to change data. the sector group unprotection mode is activated by setting the reset pin to high voltage (v id ). during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group ad- dresses. once the v id is taken away from the reset pin, all the previously protected sector groups will be protected again. refer to temporary sector group unprotection timing diagram in n switching wave- forms and temporary sector group unprotection algorithm in n flow chart. hardware reset the devices may be reset by driving the reset pin to v il from v ih . the reset pin has a pulse requirement and has to be kept low (v il ) for at least t rp in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode t ready after the reset pin is driven low. furthermore, once the reset pin goes high, the devices require an additional t rh before it will allow read access. when the reset pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. write protect (wp ) the write protection function provides a hardware method of protecting certain outermost 8k bytes / 4k words sectors without using v id . this function is one of two provided by the wp /acc pin. if the system asserts v il on the wp /acc pin, the device disables program and erase functions in the outermost 8k bytes / 4k words sectors independently of whether this sector was protected or unprotected using the method described in sector group protection" above. if the system asserts v ih on the wp /acc pin, the device reverts of whether the outermost 8k bytes / 4k words sectors were last set to be protected to the unprotected status. sector protection or unprotection for this sector depends on whether this was last protected or unprotected using the method described in sector protection/ unprotection. accelerated program operation the device offers accelerated program operation which enables programming in high speed. if the system asserts v acc to the wp /acc pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 85%. this function is primarily intended to allow high speed programing, so caution is needed as the sector group becomes temporarily unprotected. the system would use a fast program command sequence when programming during acceleration mode. set command to fast mode and reset command from fast mode are not necessary. when the device enters the acceleration mode, the device is automatically set to fast mode. therefore, the present sequence could be used for programming and detection of completion during acceleration mode. removing v acc from the wp /acc pin returns the device to normal operation. do not remove v acc from the wp / acc pin while programming. see accelerated program timing diagram in n switching waveform.
mbm29pl32tm/bm 90/10 25 n command definitions device operations are selected by writing specific address and data sequences into the command register. mbm29pl32tm/bm standard command definitions in n device bus operation shows the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. also the program suspend (b0h) and program resume (30h) commands are valid only while the program operation is in progress.moreover reset commands are functionally equivalent, resetting the device to the read mode. please note that commands must be asserted to dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read mode, the reset operation is initiated by writing the reset command sequence into the command register. the devices remain enabled for reads until the command register contents are altered. the devices will automatically be in the reset state after power-up. in this case, a command sequence is not required in order to read data. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. therefore, manufacture and device codes must be accessible while the devices reside in the target system. prom pro- grammers typically access the signature codes by raising a 9 to a high voltage. however applying high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated first by writing two unlock cycles. this is followed by a third write cycle that contains the address and the autoselect command. then the manufacture and device codes can be read from the address, and an actual data of memory cell can be read from the another address. following the command write, a read cycle from address 00h returns the manufacturess code (fujitsu = 04h). a read cycle at address 01h outputs device code. when 227eh is output, it indicates that two additional codes, called extended device codes will be required. therefore the system may continue reading out these extended device codes at address of 0eh as well as at 0fh. notice that above applies to word mode. the addresses and codes differ from those of byte mode. refer to sector group protection verify autoselect codes in n device bus operation. to terminate the operation, it is necessary to write the reset command into the register. to execute the autoselect command during the operation, reset command must be written before the autoselect command. programming the devices are programmed on a word-by-word basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) starts programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling), dq 6 (toggle bit) or ry/by . the data polling and toggle bit are automatically performed at the memory location being programmed. the programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which the devices return to the read mode and plogram addresses are no longer latched. therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance. hence data polling requires the same address which is being programmed. if hardware reset occurs during the programming operation, the data being written is not guaranteed.
mbm29pl32tm/bm 90/10 26 programming is allowed in any address sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may result in either failure condition or an apparent success according to the data polling algorithm. but a read from reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. note that attempting to program a 1 over a 0 will result in programming failure. this precaution is the same with fujitsu standard nor devices. embedded program tm algorithm in n flow chart illustrates the em- bedded program tm algorithm using typical command strings and bus operations. program suspend/resume the program suspend command allows the system to interrupt a program operation so that data can be read from any address. writing the program suspend command (b0h) during embedded program operation imme- diately suspends the programming. when the program suspend command is written during a programming process, the device halts the program operation within 1us and updates the status bits.after the program operation has been suspended, the system can read data from any address. the data at program-suspended address is not valid. normal read timing and command definitions apply. after the program resume command (30h) is written, the device reverts to programming. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see "write operation status" for more information. when issuing program suspend command in 4 m s after issuing program command, determine the status of program operation by reading status bit at more 4 m s after issuing program resume command. the system also writes the autoselect command sequence in the program suspend mode. the device allows reading autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see "autoselect command sequence" for more information. the system must write the program resume command to exit from the program suspend mode and continue the programming operation. further writes of the resume command are ignored. another program suspend command can be written after the device resumes programming. do not read cfi code after hiddenrom entry and exit in program suspend mode. write buffer programming operations write buffer programming allows the system write to series of 16 words in one programming operation. this results in faster effective word programming time than the standard programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle selecting the sector address in which programming will occur. in forth cycle contains both sector address and unique code for data bus width will be loaded into the page buffer at the sector address in which programming will occur. the system then writes the starting address/data combination. this starting address must be the same sector address used in third and fourth cycles and its lower addresses of a 3 to a 0 should be 0h. all subsequent address must be incremented by 1. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) starts programming. upon executing the write buffer programming operations com- mand sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. dq 7 (data polling), dq 6 (toggle bit), dq 5 (exceeded timing limits), dq 1 (write-to-buffer abort) should be moni- tored to determine the device status during write buffer programming. in addition to these functions, it is also possible to indicate to the host system that write buffer programming operations are either in progress or have been completed by ry/by . see hardware sequence flags. the data polling techniques described in data polling algorithm in n flow chart should be used while monitoring the last address location loaded into the write buffer. in addition, it is not neccessary to specify an
mbm29pl32tm/bm 90/10 27 address in toggle bit techniques described in toggle bit algorithm in n flow chart. the automatic pro- graming operation is completed when the data on dq7 is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched ( see "hardware sequence flags"). the write-buffer programming operation can be suspended using the standard program suspend/resume com- mands. once the write buffer programming is set, the system must then write the program buffer to flash command at the sector address. any other address/data combination will abort the write buffer programming operation and the device will continue busy state. the write buffer programming sequence can be aborted by doing the following : ? different sector address is asserted. ? write data other than the program buffer to flash" command after the specified number of data load cycles. a write-to-buffer-abort reset command sequence must be written to the device to return to read mode. (see mbm29pl32tm/bm standard command definitions in n device bus operation for details on this com- mand sequence.) chip erase chip erase is a six bus cycle operation. it begins two unlock write cycles followed by writing the set-up command, and two unlock write cycles followed by the chip erase command which invokes the embedded erase algorithm. the device does not require the user to program the device prior to erase. upon executing the embedded erase algorithm the devices automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase (preprogram function). the system is not required to provide any controls or timings during these operations. the system can determine the erase operation status by using dq 7 (data polling), dq 6 (toggle bit i ) and dq 2 (toggle bit ii) or ry/by output signal . the chip erase begins on the rising edge of the last ce or we , whichever happens first from last command sequence and completes when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read mode. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. multiple sectors may be erased concurrently by writing the same six bus cycle operations. this sequence is followed by writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than erase time-out time(t tow ). otherwise that command will not be accepted and erasure will not start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can reoccur after the last sector erase command is written. a time-out of t tow from the rising edge of last ce or we , whichever happens first, will initiate the execution of the sector erase command(s). if another falling edge of ce or we , whichever happens first occurs within the t tow time- out window the timer is reset (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer). resetting the devices once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete (refer to the write operation status). loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 70). sector erase does not require the user to program the devices prior to erase. the devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase using the embedded erase algorithm. when erasing a sector, the remaining unselected sectors remain unaffected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit) or ry/by . the sector erase begins after the t tow time-out from the rising edge of ce or we whichever happens first for the last sector erase command pulse and completes when the data on dq 7 is 1 (see write operation status section), at which the devices return to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased.
mbm29pl32tm/bm 90/10 28 erase suspend/resume the erase suspend command allows the user to interrupt sector erase operation and then perform read or programming to a sector not being erased. this command is applicable only during the sector erase operation within the time-out period for sector erase. writting the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the "erase resume" command (30h) resumes the erase operation. when the "erase suspend" command is written during the sector erase operation, the device takes maximum of t spd to suspend the erase operation. when the devices enter the erase-suspended mode, the ry/by output pin will be at high-z and the dq 7 bit will be at logic 1 and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. do not issue program command after entering erase-suspend-read mode. fast mode set/reset the device has fast mode function. it dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming consists of two cycles instead of four bus cycles in standard program command. the read operation is also executed after exiting this mode. during the fast mode, do not write any command other than the fast program/fast mode reset command. to exit from this mode, write fast mode reset command into the command register. (refer to the embedded program tm algorithm for fast mode in n flow chart.) the v cc active current is required even ce = v ih during fast mode. fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). see embedded program tm algorithm for fast mode in n flow chart. extended sector group protection in addition to normal sector group protection, the device has extended sector group protection as extended function. this function enables protection of the sector group by forcing v id on reset pin and writes a command sequence. unlike conventional procedures, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector group protection in this mode. the extended sector group protection requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then the sector group addresses pins (a 20 , a 19 , a 18 , a 17, a 16, a 15, a 14, a 13 and a 12 ) and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (set v il for the other addresses pins is recommended), and write extended sector group protection command (60h). a sector group is typically protected in 250 m s. to verify programming of the protection circuitry, the sector group addresses pins (a 20 , a 19 , a 18 , a 17, a 16, a 15, a 14, a 13 and a 12 ) and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) should be set and write a command (40h). following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output data is logical 0, write the extended sector group protection command (60h) again. to terminate the operation, set reset pin to v ih . (refer to the extended sector group protection timing diagram in n switching waveforms and extended sector group protection algorithm in n flow chart.)
mbm29pl32tm/bm 90/10 29 query command (cfi : common flash memory interface) the cfi (common flash memory interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. this allows device-independent, jedec id-independent, and forward-and backward-compatible software sup- port for the specified flash device families. refer to cfi specification in detail. the operation is initiated by writing the query command (98h) into the command register. following the command write, a read cycle from specific address retrieves device information. please note that output data of upper byte (dq 15 to dq 8 ) is 0. refer to the cfi code table. to terminate operation, it is necessary to write the reset command sequence into the register. (see common flash memory interface code in n device bus oper- ation.) hiddenrom mode (1) hiddenrom region the hiddenrom (hiddenrom) feature provides a flash memory region that the system may access through a new command sequence. this is primarily intended for customers who wish to use an electronic serial number (esn) in the device with the esn protected against modification. once the hiddenrom region is protected, any further modification of that region is impossible. this ensures the security of the esn once the product is shipped to the field. the hiddenrom region is 256 bytes / 128 words in length. after the system writes the hiddenrom entry command sequence, it may read the hiddenrom region by using device addresses a 6 to a 0 (a 20 to a 7 are all 0). that is, the device sends only program command that would normally be sent to the address to the hiddenrom region. this mode of operation continues until the system issues the exit hiddenrom command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the address. if you request fujitsu to program the esn in the device, please contact a fujitsu representative for more infor- mation. (2) hiddenrom entry command the device has a hiddenrom area with one time protect function. this area is to enter the security code and to unable the change of the code once set. programming is allowed in this area until it is protected. however, once it gets protected, it is impossible to unprotect. therefore, extreme caution is required. the hiddenrom area is 256 bytes / 128 words. this area is in sa0 . therefore, write the hiddenrom entry command sequence to enter the hiddenrom area. it is called hiddenrom mode when the hiddenrom area appears. sectors other than the block area sa0 can be read during hiddenrom mode. read/program of the hiddenrom area is possible during hiddenrom mode. write the hiddenrom reset command sequence to exit the hidden- rom mode. note that any other commands should not be issued than the hiddenrom program/protection/reset commands during the hiddenrom mode. when you issue the other commands including the suspend resume capability, send the hiddenrom reset command first to exit the hiddenrom mode and then issue each com- mand.
mbm29pl32tm/bm 90/10 30 (3) hiddenrom program command to program the data to the hiddenrom area, write the hiddenrom program command sequence during hid- denrom mode. this command is the same as the usual program command, except that it needs to write the command during hiddenrom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data pooling, dq 6 toggle bit or ry/by . you should pay attention to the address to be programmed. if an address not in the hiddenrom area is selected, the previous data will be deleted. during the write into the hiddenrom region, the program suspend command issuance is prohibited. (4) hiddenrom protect command there are two methods to protect the hiddenrom area. one is to write the sector group protect setup command (60h) , set the sector address in the hiddenrom area and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) , and write the sector group protect command (60h) during the hiddenrom mode. the same command sequence may be used because it is the same as the extension sector group protect in the past, except that it is in the hiddenrom mode and does not apply high voltage to the reset pin. please refer to above mentioned extended sector group protection for details of sector group protect setting. the other method is to apply high voltage (v id ) to a 9 and oe , set the sector address in the hiddenrom area and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) , and apply the write pulse during the hiddenrom mode. to verify the protect circuit, apply high voltage (v id ) to a 9 , specify (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) and the sector address in the hiddenrom area, and read. when 1 appears on dq 0 , the protect setting is completed. 0 will appear on dq 0 if it is not protected. apply write pulse again. the same command sequence could be used for the above method because other than the hiddenrom mode, it is the same as the sector group protect previously men- tioned. take note that other sector groups will be affected if an address other than those for the hiddenrom area is selected for the sector group address, so please be careful. pay close attention that once it is protected, protection cannot be cancelled.
mbm29pl32tm/bm 90/10 31 write operation status detailed in hardware sequence flags are all the status flags which can determine the status of the device for current mode operation. when checking hardware sequence flags during program operations, it should be checked 4 m s after issuing program command. during sector erase, the part provides the status flags automat- ically to the i/o ports. the information on dq 2 is address sensitive. if an address from an erasing sector is consecutively read, then the dq 2 bit will toggle. however dq 2 will not toggle if an address from a non-erasing sector is consecutively read. this allows the user to determine which sectors are erasing. once erase suspend is entered address sensitivity still applies. if the address of a non-erasing sector (one available for read) is provided, then stored data can be read from the device. if the address of an erasing sector (one unavailable for read) is applied, the device will output its status bits. hardware sequence flags *1 : successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. *2 : reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. *3 : dq 1 indicates the write-to-buffer abort status during write-buffer-programming operations. *4 : the data polling algorithm detailed in data polling algorithm in n flow chart should be used for write- buffer-programming operations. note that dq 7 during write-buffer-programming indicates the data-bar for dq 7 data for the last loaded write-buffer address location. status dq 7 dq 6 dq 5 dq 3 dq 2 dq 1 * 3 in progress embedded program algorithm dq 7 toggle 0 0 1 0 embedded erase algorithm 0 toggle 0 1 toggle* 1 n/a program suspend mode program-suspend-read (program suspended sector) data data data data data data program-suspend-read (non-program suspended sector) data data data data data data erase suspend mode erase-suspend-read (erase suspended sector) 1 1 0 0 toggle* 1 n/a erase-suspend-read (non-erase suspended sector) data data data data data data erase-suspend-program (non-erase suspended sector) dq 7 toggle 0 0 1* 2 n/a exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 n/a embedded erase algorithm 0 toggle 1 1 n/a n/a erase suspend mode erase-suspend-program (non-erase suspended sector) dq 7 toggle 1 0 n/a n/a write to buffer* 4 busy state dq 7 toggle 0 n/a n/a 0 exceeded timing limits dq 7 toggle 1 n/a n/a 0 abort state n/a toggle 0 n/a n/a 1
mbm29pl32tm/bm 90/10 32 dq 7 data polling the devices feature data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read devices will produce reverse data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm, an attempt to read device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in data polling algorithm in n flow chart. for programming, the data polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. data polling must be performed at sector addresses of sectors being erased, not protected sectors. otherwise, the status may become invalid. if a program address falls within a protected sector, data polling on dq7 is active for approximately 1 m s, then the device returns to read mode. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq 7 is active for approximately 100 m s, then the device returns to read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. once the embedded algorithm operation is close to being completed, the device data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq 7 at one instant of time, and then that bytes valid data the next. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device completes the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 6 to dq 0 may still be invalid. the valid data on dq 7 to dq 0 will be read on the successive read attempts. the data polling feature is active only during the embedded programming algorithm, embedded erase algo- rithm, erace suspendmode or sector erase time-out. see data polling during embedded algorithm operation timing diagram in n switching waveform for the data polling timing specifications and diagram. dq 6 toggle bit i the device also feature the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (ce or oe toggling) data from the devices will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequences. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequences. the toggle bit i is active during the sector time out. in programm operation, if the sector being written to is protected, the toggle bit will toggle for about 1 m s and then stop toggling with the data unchanged. in erase, the device will erase all the selected sectors except for the protected ones. if all selected sectors are protected, the chip will toggle the toggle bit for about 100 m s and then drop back into read mode, having data kept remained. either ce or oe toggling will cause the dq 6 to toggle. see toggle bit l timing diagramduring embedded algorithm operations in n switching waveform for the toggle bit i timing specifications and diagram.
mbm29pl32tm/bm 90/10 33 dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition indicating that the program or erase cycle was not successfully completed. data polling is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in mbm29pl32tm/bm user bus operations (word mode : byte = vih) and mbm29pl32tm/bm user bus operations (byte mode : byte = vil) in n device bus operation. the dq 5 failure condition may also appear if a user tries to program a non blank location without pre-erase. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stop toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a 1. note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates a valid erase command has been written, dq 3 may be used to determine whether the sector erase timer window is still open. if dq 3 is 1 the internally controlled erase cycle has begun. if dq 3 is 0, the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see hardware sequence flags. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows: for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also hardware sequence flags and dq 2 vs. dq 6 in n switching waveform. furthermore, dq 2 can also be used to determine which sector is being erased. at the erase mode, dq 2 toggles if this bit is read from an erasing sector.
mbm29pl32tm/bm 90/10 34 reading toggle bits dq 6 / dq 2 whenever the system initially begins reading toggle bit status, it must read dq 7 to dq 0 at least twice in a row to determine whether a toggle bit is toggling. typically a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq 7 to dq 0 on the following read cycle. however, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq 5 is high (see the section on dq 5 ) . if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq 5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, deter- mining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (refer to toggle bit algorithm in n flow chart.) toggle bit status *1 : successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. *2 : reading from the non-erase suspend sector address will indicate logic 1 at the dq 2 bit. dq 1 write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a "1". the system must issue the write-to-buffer-abort-reset command sequence to return the device to reading array data. see "write buffer programming operations" section for more details. ry/by ready/busy the device provides a ry/by open-drain output pin to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the device is busy with either a program or erase operation. if the output is high, the device is ready to accept any read/write or erase operation. if the device is placed in an erase suspend mode, the ry/by output will be high, by means of connecting with a pull- up resister to v cc . during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin will indicate a busy condition during the reset pulse. see ry/by timing diagram during program/erase operation timing diagram and reset timing diagram ( during embedded algorithms ) in n switching waveform for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle * 1 erase-suspend-read (erase-suspended sector) 1 1 toggle * 1 erase-suspend-program dq 7 toggle 1 * 2
mbm29pl32tm/bm 90/10 35 word/byte configuration byte pin selects the byte (8-bit) mode or word (16-bit) mode for the device. when this pin is driven high, the device operates in the word (16-bit) mode. data is read and programmed at dq 15 to dq 0 . when this pin is driven low, the device operates in byte (8-bit) mode. in this mode, dq 15 /a -1 pin becomes the lowest address bit, and dq 14 to dq 8 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence com- mands are written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. data protection the device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the device automatically reset the internal state machine in read mode. also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. (1) low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than v lko . if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition, the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above v lko . if embedded erase algorithm is interrupted, the intervened erasing sector(s) is(are) not valid. (2) write pulse glitch protection noise pulses of less than 3 ns (typical) on oe , ce , or we will not initiate a write cycle. (3) logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write, ce and we must be a logical zero while oe is a logical one. (4) power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to read mode on power-up. (5) sector protection device user is able to protect each sector group individually to store and protect data. protection circuit voids both write and erase commands that are addressed to protected sectors. any commands to write or erase addressed to protected sector are ignored .
mbm29pl32tm/bm 90/10 36 n absolute maximum ratings *1 : voltage is defined on the basis of vss = gnd = 0 v. *2 : minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to C0.2 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods of up to 20 ns *3 : minimum dc input voltage is C0.5v. during voltage transitions, these pins may undershoot v ss to C0.2 v for periods of up to 20 ns.voltage difference between input and supply voltage ( v in Cv cc ) dose not exceed to +9.0 v. maximum dc input voltage is +12.5 v which may overshoot to +14.0 v for periods of up to 20 ns . warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions * : voltage is defined on the basis of v ss = gnd = 0v. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg C55 +125 c ambient temperature with power applied t a C20 +85 c voltage with respect to ground all pins except a 9 , oe , and reset * 1, * 2 v in , v out C0.5 v cc +0.5 v power supply voltage * 1 v cc C0.5 +4.0 v input voltage a 9 , oe , and reset * 1, * 3 v in C0.5 +12.5 v input voltage wp /acc * 1, * 3 v acc C0.5 +12.5 v parameter symbol value unit min max ambient temperature 90 t a C20 +70 c 10 C20 +85 v cc supply voltage * v cc +3.0 +3.6 v
mbm29pl32tm/bm 90/10 37 n maximum overshoot/maximum undershoot maximum undershoot waveform +0.6 v C0.5 v 20 ns C2.0 v 20 ns 20 ns maximum overshoot waveform 1 0.7 v cc v cc +0.5 v 20 ns v cc +2.0 v 20 ns 20 ns maximum overshoot waveform 2 v cc +0.5 v +12.5 v 20 ns +14.0 v 20 ns 20 ns note: this waveform is applied for a 9 , oe , reset , and acc.
mbm29pl32tm/bm 90/10 38 n electrical characteristics 1. dc characteristics *1 : the l cc current listed includes both the dc operating current and the frequency dependent component. *2 : maximum i cc values are tested with v cc = v cc max *3 : i cc active while embedded erase or embedded program or write buffer programming is in progress. *4 : automatic sleep mode enables the low power mode when address remain stable for t acc + 30 ns. parameter symbol conditions value unit min typ max input leakage current i li v in = v ss to v cc , v cc = v cc max wp /acc pin C2.0 +2.0 a others C1.0 +1.0 output leakage current i lo v out = v ss to v cc , v cc = v cc max C1.0 +1.0 a a 9 , oe , reset inputs leakage current i lit v cc = v cc max, a 9 , oe , reset = 12.5 v 35a v cc active current (read ) * 1, * 2 i cc1 ce = v il , oe = v ih , f = 5 mhz word 18 20 ma byte 16 20 ce = v il , oe = v ih , f = 10 mhz word 35 50 byte 35 50 v cc active current (intra-page read ) * 2 i cc2 ce = v il , oe = v ih , t prc = 25ns, 4-word 1020ma v cc active current (program / erase) * 2, * 3 i cc3 ce = v il , oe = v ih 5060ma v cc standby current * 2 i cc4 ce = v cc 0.3 v, reset = v cc 0.3 v, oe = v ih , wp /acc = v cc 0.3 v 1 5a v cc reset current * 2 i cc5 reset = v cc 0.3 v, wp /acc = v cc 0.3 v 1 5a v cc automatic sleep current * 4 i cc6 ce = v ss 0.3 v, reset = v cc 0.3 v, v in = v cc 0.3v or v ss 0.3v, wp /acc = v cc 0.3 v 1 5a v cc active current (erase-suspend-program) * 2 i cc7 ce = v il , oe = v ih 5060ma acc accelerated program current i acc ce = v il , oe = v ih , vcc = vcc max, wp /acc =v acc max wp /acc pin 20 ma vcc pin 60 input low level v il C0.5 0.6 v input high level v ih 0.7 v cc v cc + 0.3 v voltage for wp /acc sector protection/unprotection and program acceleration v acc v cc = 3.0 v to 3.6 v 11.5 12.0 12.5 v voltage for autoselect, and temporary sector unprotected v id v cc = 3.0 v to 3.6 v 11.5 12.0 12.5 v output low voltage level v ol i ol = 4.0 ma, v cc = v cc min 0.45 v output high voltage level v oh i oh = C2.0 ma, v cc = v cc min 0.85 v cc v low v cc lock-out voltage v lko 2.32.5v
mbm29pl32tm/bm 90/10 39 2. ac characteristics ? read only operations characteristics * : test conditions : output load : 1 ttl gate and 30 pf input rise and fall times : 5 ns input pulse levels : 0.0 v or v cc timing measurement reference level input : v cc / 2 output : v cc / 2 parameter symbols condition value* unit 90 10 jedec standard min max min max read cycle time t avav t rc 90 ? 100 ? ns address to output delay t avqv t acc ce = v il, oe = v il ? 90 ? 100 ns chip enable to output delay t elqv t ce oe = v il ? 90 ? 100 ns page read cycle time t prc 25 ? 30 ? ns page address to output delay t pacc ce = v il, oe = v il ? 25 ? 30 ns output enable to output delay t glqv t oe ? 25 ? 30 ns chip enable to output high-z t ehqz t df ? 25 ? 30 ns output enable hold time read t oeh 0 ? 0 ? ns toggle and data polling 10 ? 10 ? ns output enable to output high-z t ghqz t df ? 25 ? 30 ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh 0 ? 0 ? ns reset pin low to read mode t ready ? 20 ? 20 s test conditions c l 3.3 v diode = 1n3064 or equivalent 2.7 k w device under test diode = 1n3064 or equivalent 6.2 k w
mbm29pl32tm/bm 90/10 40 ? write (erase/program) operations (continued) parameter symbol value unit 90 10 jedec standard min typ max min typ max write cycle time t avav t wc 90 ?? 100 ?? ns address setup time t avwl t as 0 ?? 0 ?? ns address setup time to oe low during toggle bit polling t aso 15 ?? 15 ?? ns address hold time t wlax t ah 45 ?? 45 ?? ns address hold time from ce or oe high during toggle bit polling t aht 0 ?? 0 ?? ns data setup time t dvwh t ds 35 ?? 35 ?? ns data hold time t whdx t dh 0 ?? 0 ?? ns oe setup time t oes 0 ?? 0 ?? ns ce high during toggle bit polling t ceph 20 ?? 20 ?? ns oe high during toggle bit polling t oeph 20 ?? 20 ?? ns read recover time before write (oe high to we low) t ghwl t ghwl 0 ?? 0 ?? ns read recover time before write (oe high to ce low) t ghel t ghel 0 ?? 0 ?? ns ce setup time t elwl t cs 0 ?? 0 ?? ns we setup time t wlel t ws 0 ?? 0ns ce hold time t wheh t ch 0 ?? 0 ?? ns we hold time t ehwh t wh 0 ?? 0 ?? ns ce pulse width t eleh t cp 35 ?? 35 ?? ns write pulse width t wlwh t wp 35 ?? 35 ?? ns ce pulse width high t ehel t cph 25 ?? 25 ?? ns write pulse width high t whwl t wph 30 ?? 30 ?? ns effective page programming time (write buffer programming) per word t whwh1 t whwh1 ? 23.5 ?? 23.5 ? s programming time word ? 100 ?? 100 ? s sector erase operation * 1 t whwh2 t whwh2 ? 1.0 ?? 1.0 ? s v cc setup time t vcs 50 ?? 50 ?? s recovery time from ry/by t pb 0 ?? 0 ?? ns erase/program valid to ry/by delay t busy ?? 90 ?? 90 ns rise time to v id * 2 t vidr 500 ?? 500 ?? ns rise time to v acc * 3 t vaccr 500 ?? 500 ?? ns voltage transition time * 2 t vlht 4 ?? 4 ?? s
mbm29pl32tm/bm 90/10 41 (continued) *1 : this does not include the preprogramming time. *2 : this timing is for sector group protection operation. *3 : this timing is for accelerated program operation. parameter symbol value unit 90 10 jedec standard min typ max min typ max write pulse width * 2 t wpp 100 ?? 100 ?? s oe setup time to we active * 2 t oesp 4 ?? 4 ?? s ce setup time to we active * 2 t csp 4 ?? 4 ?? s reset pulse width t rp 500 ?? 500 ?? ns reset high time before read t rh 100 ?? 100 ?? ns delay time from embedded output enable t eoe ?? 90 ?? 100 ns erase time-out time t tow 50 ?? 50 ?? s erase suspend transition time t spd ?? 20 ?? 20 s
mbm29pl32tm/bm 90/10 42 n erase and programming performance n tsop (1) pin capacitance notes : test conditions t a = + 25c, f = 1.0 mhz dq 15 /a- 1 pin capacitance is stipulated by output capacitance. n fbga pin capacitance notes : test conditions t a = + 25c, f = 1.0 mhz dq 15 /a- 1 pin capacitance is stipulated by output capacitance. parameter limits unit remarks min typ max sector erase time 1 15 s excludes programming time prior to erasure programming time 100 3000 s excludes system-level overhead effective page programming time (write buffer programming) 23.5 s chip programming time 300 s absolute maximum programming time (16 words) 6ms non programming within the same page erase/program cycle 100,000 cycle parameter symbol test setup value unit min typ max input capacitance c in v in = 0 8 10 pf output capacitance c out v out = 0 8.5 12 pf control pin capacitance c in2 v in = 0 8 10 pf reset pin and wp /acc pin capacitance c in3 v in = 0 20 25 pf parameter symbol test setup value unit min typ max input capacitance c in v in = 0 8 10 pf output capacitance c out v out = 0 8.5 12 pf control pin capacitance c in2 v in = 0 8 10 pf reset pin and wp /acc pin capacitance c in3 v in = 0 15 20 pf
mbm29pl32tm/bm 90/10 43 n switching waveforms ? key to switching waveforms read operation timing diagram waveform inputs outputs must be steady may change from h to l may change from l to h ??or ? any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing state unknown center line is high- impedance ?ff?state we oe ce t acc t df t ce t oh t oe data t rc address address stable high-z output valid high-z t oeh
mbm29pl32tm/bm 90/10 44 reset t acc t oh data t rc address address stable high-z output valid t rh ce t rp t rh t ce data a 1 to a 0 (a -1 ) a 20 to a 2 ce oe we aa ab ac t rc t acc t ce t oe t oh t oh t oh t df t pacc t pacc t oeh t prc da db dc address valid high-z page read operation timing diagram hardware reset/read operation timing diagram
mbm29pl32tm/bm 90/10 45 notes : pa is address of the memory location to be programmed. pd is data to be programmed at word address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycle sequence. t ch t wp t whwh1 t wc t ah ce oe t rc address data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out t df alternate we controlled program operation timing diagram
mbm29pl32tm/bm 90/10 46 t cp t ds t whwh1 t wc t ah we oe address data t as t cph t dh dq 7 a0h d out ce 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd notes : pa is address of the memory location to be programmed. pd is data to be programmed at word address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycle sequence. alternate ce controlled program operation timing diagram
mbm29pl32tm/bm 90/10 47 address data v cc ce oe we 555h 2aah 555h 555h 2aah sa* t wc t as t ah t cs t ghwl t ch t wp t ds t vcs t dh t wph aah 55h 80h aah 55h 10h/ 30h 10h for chip erase ry/by t busy sa* 30h t tow * : sa is the sector address for sector erase. address = 555h (word), aaah (byte) for chip erase. chip/sector erase operation timing diagram
mbm29pl32tm/bm 90/10 48 address data ce we xxxh t wc t cs t ch t wp t ds b0h ry/by t spd erase suspend operation timing diagram
mbm29pl32tm/bm 90/10 49 t oeh t ch t oe t ce t df t eoe t busy t whwh1 or 2 ce dq 7 ry/by dq 6 to dq 0 dq 7 dq 7 = valid data dq 6 to dq 0 = output flag dq 6 to dq 0 valid data oe we address high-z high-z data data * va 4 m s * : dq 7 = valid data (the device has completed the embedded operation.) note : when checking hardware sequence flags during program operations, it should be checked 4 m s after issuing program command. data polling during embedded algorithm operation timing diagram
mbm29pl32tm/bm 90/10 50 * : dq 6 stops toggling (the device has completed the embedded operation). note : when checking hardware sequence flags during program operations, it should be checked 4 m s after issuing program command. t dh t oe t ce ce we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh 4 m s t oeph t aht t aht t aso t as t ceph toggle bit l timing diagram during embedded algorithm operations * : dq 2 is read from the erase-suspended sector. dq 2 * dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with o e or ce dq 2 vs. dq 6
mbm29pl32tm/bm 90/10 51 rising edge of the last we signal ce ry/by we t busy entire programming or erase operations ry/by timing diagram during program/erase operation timing diagram reset t ready ce , oe t rh t rp reset timing diagram ( not during embedded algorithms )
mbm29pl32tm/bm 90/10 52 t rp reset t ready ry/by we t rb reset timing diagram ( during embedded algorithms )
mbm29pl32tm/bm 90/10 53 t vlht sgax a 20 , a 19 , a 18 , a 17 , a 16 a 15 , a 14 , a 13 , a 12 sgay a 6 , a 3 , a 2 , a 0 a 9 v ih t vlht oe v ih t vlht t vlht t oesp t wpp t csp we ce t oe 01h data v cc a 1 t vcs v id v id sgax : sector group address to be protected sgay : next sector group address to be protected sector group protection timing diagram
mbm29pl32tm/bm 90/10 54 reset ce we ry/by t vlht program or erase command sequence t vlht t vidr v id unprotection period t vcs t vlht v cc v ss , v il or v ih temporary sector group unprotection timing diagram
mbm29pl32tm/bm 90/10 55 sgax: sector group address to be protected sgay : next sector group address to be protected time-out : time-out window = 250 m s (min) sgay reset oe we ce data a 1 v cc a 6 , a 3 , a 2 , a 0 address sgax sgax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe extended sector group protection timing diagram
mbm29pl32tm/bm 90/10 56 v cc ce we t vlht program command sequence t vlht t vcs t vaccr v acc t vlht acceleration period acc accelerated program timing diagram
mbm29pl32tm/bm 90/10 57 n flow chart 555h/aah 555h/a0h 2aah/55h program address/program data programming completed last address ? increment address verify data ? data polling program command sequence (address/command) : write program command sequence (see below) start no no yes yes embedded program algorithm in progress embedded algorithms note : the sequence is applied for word ( 16 ) mode. the addresses differ from byte ( 8 ) mode. embedded program tm algorithm
mbm29pl32tm/bm 90/10 58 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah sector address /30h sector address /30h sector address /30h 2aah/55h erasure completed data = ffh ? data polling write erase command sequence (see below) start no yes embedded erase algorithm in progress chip erase command sequence (address/command) : individual sector/multiple sector erase command sequence (address/command) : additional sector erase commands are optional. embedded algorithms note : the sequence is applied for word ( 16 ) mode. the addresses differ from byte ( 8 ) mode. embedded erase tm algorithm
mbm29pl32tm/bm 90/10 59 dq 7 = data? * no no dq 7 = data? dq 5 = 1? yes yes no read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va yes start fail pass wait 4 m s after issuing program command * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . note : data polling on sector-group protected sector may fail. va = valid address for programming = any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = any of the sector addresses within the sector not being protected during chip erase operation data polling algorithm
mbm29pl32tm/bm 90/10 60 *1 : read toggle bit twice to determine whether it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changes to 1. dq 6 = toggle dq 5 = 1? read dq 7 to dq 0 addr. = "h" or "l" read dq 7 to dq 0 addr. = "h" or "l" read dq 7 to dq 0 addr. = "h" or "l" start no no yes yes *1 *1, *2 ? no yes program/erase operation not complete.write reset command program/erase operation complete dq 6 = toggle ? read dq 7 to dq 0 addr. = "h" or "l" *1 wait 4 m s after issuing program command toggle bit algorithm
mbm29pl32tm/bm 90/10 61 start no no no yes yes yes data = 01h? device failed plscnt = 25? plscnt = 1 remove v id from a 9 write reset command remove v id from a 9 write reset command sector group protection completed protect another sector group? increment plscnt read from sector group addr. = sga, a 1 = v ih a 6 = a 3 = a 2 = a 0 = v il setup sector group addr. (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 ) oe = v id , a 9 = v id ce = v il , reset = v ih a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih activate we pulse time out 100 m s we = v ih , ce = oe = v il (a 9 should remain v id ) () * * : a -1 is v il in byte ( 8 ) mode. sector group protection algorithm
mbm29pl32tm/bm 90/10 62 reset = v id *1 perform erase or program operations reset = v ih start temporary sector group unprotection completed *2 *1 : all protected sector groups are unprotected. *2 : all previously protected sector groups are protected. temporary sector group unprotection algorithm
mbm29pl32tm/bm 90/10 63 to protect sector group yes no no plscnt = 1 protection other sector start sector group protection extended sector group completed remove v id from reset write reset command reset = v id wait to 4 m s protection entry? to setup sector group protection write xxxh/60h write 60h to sector address (a 6 = a 3 = a 2 = a 0 =v il , a 1 = v ih ) time out 250 m s to verify sector group protection write 40h to sector address (a 6 = a 3 = a 2 = a 0 =v il , a 1 = v ih ) data = 01h? group? device is operating in temporary sector group read from sector group ( a 6 = a 3 = a 2 = a 0 =v il , a 1 = v ih ) increment plscnt no yes yes unprotection mode address setup next sector group address no yes plscnt = 25? device failed remove v id from reset write reset command extended sector group protection algorithm
mbm29pl32tm/bm 90/10 64 fast mode algorithm start 555h/aah 2aah/55h xxxh/a0h 555h/20h verify data? no program address/program data data polling last address ? programming completed xxxh/90h xxxh/f0h increment address no yes yes set fast mode in fast program reset fast mode notes : the sequence is applied for word ( 16 ) mode. the addresses differ from byte ( 8 ) mode. embedded program tm algorithm for fast mode
mbm29pl32tm/bm 90/10 65 n ordering information part no. package access time (ns) remarks MBM29PL32TM90TN 48-pin, plastic tsop (1) (fpt-48p-m19) (normal bend) 90 ns top sector mbm29pl32tm10tn 100 ns mbm29pl32tm90pbt 48-ball, plastic fbga (bga-48p-m20) 90 ns mbm29pl32tm10pbt 100 ns mbm29pl32bm90tn 48-pin, plastic tsop (1) (fpt-48p-m19) (normal bend) 90 ns bottom sector mbm29pl32bm10tn 100 ns mbm29pl32bm90pbt 48-ball, plastic fbga (bga-48p-m20) 90 ns mbm29pl32bm10pbt 100 ns mbm29pl32tm/bm device number/description 32 mbit (4m 8/2m 16) mirrorflash with page mode, boot sector 3.0 v-only read, program, and erase package type tn = 48-pin thin small outline package (tsop(1) standard pinout) pbt = 48-ball fine pitch ball grid array package (fbga) 90 tn speed option 90 = 90 ns access time 10 = 100 ns access time
mbm29pl32tm/bm 90/10 66 n package dimensions (continued) 48-pin plastic tsop(1) (fpt-48p-m19) note 1) * : values do not include resin protrusion. resin protrusion and gate protrusion are +0.15(.006)max(each side). note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. C .003 +.001 C 0.08 +0.03 .007 0.17 "a" (stand off height) 0.10(.004) (mounting height) (.472 .008) 12.00 0.20 lead no. 48 25 24 1 (.004 .002) 0.10(.004) m 1.10 +0.10 C 0.05 +.004 C .002 .043 0.10 0.05 (.009 .002) 0.22 0.05 (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2003 fujitsu limited f48029s-c-6-7 c 0~8 ? 0.25(.010) 0.50(.020) 0.60 0.15 (.024 .006) details of "a" part * *
mbm29pl32tm/bm 90/10 67 (continued) 48-ball plastic fbga (bga-48p-m20) dimensions in mm (inches) note : the values in parentheses are reference values. c 2003 fujitsu limited b48020s-c-2-2 8.00 0.20(.315 .008) 0.38 0.10(.015 .004) (stand off) (mounting height) 6.00 0.20 (.236 .008) 0.10(.004) 0.80(.031)typ 5.60(.220) 4.00(.157) 48- ? 0.45 0.05 (48- ? .018 .002) m ? 0.08(.003) h g fed c ba 6 5 4 3 2 1 .043 C .005 +.003 C 0.13 +0.12 1.08 (index area)
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